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december 2007 rev 3 1/14 14 STS9D8NH3LL dual n-channel 30 v - 0.012 ? - 9 a - so-8 low on-resistance stripfet? power mosfet features optimal r ds (on) x qg trade-off @ 4.5v conduction losses reduced switching losses reduced application switching applications description this device uses the latest advanced design rules of st?s strip based technology. the q1 and q2 transistors, show respectively, the best gate charge and on-resistance for minimizing the switching and conduction losses. this application specific power mosfet has been designed to replace two so-8 packages in dc-dc converters. figure 1. internal schematic diagram type v dss r ds(on) qg i d STS9D8NH3LL q 1 30v < 0.022 ? 7nc 8a q 2 30v < 0.015 ? 8nc 9a s0-8 table 1. device summary order code marking package packaging STS9D8NH3LL 9d8h3ll- so-8 tape & reel www.st.com
contents STS9D8NH3LL 2/14 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STS9D8NH3LL ele ctrical ratings 3/14 1 electrical ratings table 2. absolute maximum ratings symbol parameter type value unit v ds drain-source voltage (v gs = 0) q 1 q 2 30 30 v v v gs gate- source voltage q 1 q 2 16 16 v v i d drain current (continuous) at t c = 25c q 1 q 2 8 9 a a i d drain current (continuous) at t c = 100c q 1 q 2 5 6.3 a a i dm (1) 1. pulse width limited by safe operating area drain current (pulsed) q 1 q 2 32 36 a a p tot total dissipation at t c = 25c q 1 q 2 2 2 w w e as (2) 2. starting t j = 25 c, i d = 7.5 a single pulse avalanche energy 150 mj table 3. thermal data symbol parameter value unit r thj-a (1) 1. when mounted on 1 inch2 fr-4 board, 2 oz. cu., t < 10s thermal resistance juncti on-ambient max 62.5 c/w t j thermal operating junction-ambient 150 c t stg storage temperature -55 to 150 c
electrical characteristics STS9D8NH3LL 4/14 2 electrical characteristics (t case =25c unless otherwise specified) table 4. on/off states symbol parameter test conditions type min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 q 1 q 2 30 30 v v i dss zero gate voltage drain current (v gs = 0) v ds = max rating q 1 q 2 1 1 a a i dss zero gate voltage drain current (v gs = 0) v ds =max rating @125c q 1 q 2 10 10 a a i gss gate-body leakage current (v ds = 0) v gs = 16 v q 1 q 2 100 100 na na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a q 1 q 2 1 1 v v r ds(on) static drain-source on resistance v gs = 10 v, i d = 4 a v gs = 10 v, i d = 4.5 a q 1 q 2 0.018 0.012 0.022 0.015 ? ? r ds(on) static drain-source on resistance v gs = 4.5 v, i d = 4 a v gs = 4.5 v, i d = 4.5 a q 1 q 2 0.020 0.014 0.025 0.0175 ? ? table 5. dynamic symbol parameter test conditions type min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 q 1 q 2 857 1070 pf pf c oss output capacitance q 1 q 2 147 290 pf pf c rss reverse transfer capacitance q 1 q 2 20 34 pf pf q g total gate charge v dd = 15 v, i d = 8 a, v gs = 4.5 v (see figure 25) q 1 q 2 7 8 10 11 nc nc q gs gate-source charge q 1 q 2 2.5 2 nc nc q gd gate-drain charge q 1 q 2 2.3 2.8 nc nc
STS9D8NH3LL electrical characteristics 5/14 table 6. switching times symbol parameter test conditions type min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =15 v, i d =4 a, r g =4.7 ?, v gs = 4.5 v (see figure 27) q 1 q 2 q 1 q 2 12 8.2 14.5 6 ns ns ns ns t d(off) t f turn-off delay time fall time v dd =15 v, i d =4 a, r g =4.7 ?, v gs = 4.5v (see figure 27) q 1 q 2 q 1 q 2 23 27.8 8 3.6 ns ns ns ns table 7. source drain diode symbol parameter test conditions type min typ. max unit i sd source-drain current v dd =15 v, i d =4 a r g =4.7 ? , v gs =4.5 v q 1 q 2 8 9 a a i sdm (1) 1. pulse width limited by safe operating area. source-drain current (pulsed) v dd =15 v, i d = 4a r g =4.7 ? , v gs =4.5 v q 1 q 2 32 36 a a v sd (2) 2. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 8 a, v gs = 0 q 1 q 2 1.5 1.5 v v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 8 a, v dd = 15 v di/dt = 100 a/s, t j = 150c (see figure 26) q 1 q 2 q 1 q 2 q 1 q 2 15 22.8 5.7 14.9 0.76 1.3 ns ns nc nc a a
electrical characteristics STS9D8NH3LL 6/14 2.1 electrical characteristics (curves) figure 2. safe operating area for q1 figure 3. safe operating area for q2 figure 4. thermal impedance for q1 figure 5. thermal impedance for q2 figure 6. output characteristics for q1 figure 7. output characteristics for q2
STS9D8NH3LL electrical characteristics 7/14 figure 8. transfer characteristics for q1 figure 9. transfer characteristics for q2 figure 10. static drain-source on resistance for q1 figure 11. static drain-source on resistance for q2 figure 12. normalized bv dss vs temperature for q1 figure 13. normalized bv dss vs temperature for q2
electrical characteristics STS9D8NH3LL 8/14 figure 14. gate charge vs gate-source voltage for q1 figure 15. gate charge vs gate-source voltage for q2 figure 16. capacitance variations for q1 figure 17. capacitance variations for q2 figure 18. normalized gate threshold voltage vs temperature for q1 figure 19. normalized gate threshold voltage vs temperature for q2
STS9D8NH3LL electrical characteristics 9/14 figure 20. normalized on resistance vs temperature for q1 figure 21. normalized on resistance vs temperature for q2 figure 22. source-drain diode forward characteristics for q1 figure 23. source-drain diode forward characteristics for q2
test circuit STS9D8NH3LL 10/14 3 test circuit figure 24. switching times test circuit for resistive load figure 25. gate charge test circuit figure 26. test circuit for inductive load switching and diode recovery times figure 27. unclamped inductive load test circuit figure 28. unclamped inductive wavefo rm figure 29. switching time waveform
STS9D8NH3LL package mechanical data 11/14 4 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
package mechanical data STS9D8NH3LL 12/14 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m 0.6 0.023 s 8 (max.) so-8 mechanical data
STS9D8NH3LL revision history 13/14 5 revision history table 8. document revision history date revision changes 05-jan-2007 1 first release 06-mar-2007 2 some value changed on ta b l e 4 (r ds(on) for q2) 10-dec-2007 3 added e as value on table 2: absolute maximum ratings
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